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KL5KUSB220
USB2.0 to 100 Ethernet Controller General Description
The Kawasaki KL5KUSB220 Controller used in conjunction with the KL5KUSB200/201 USB2.0 transceiver is a unique solution to interface peripheral devices to the Universal Serial Bus 2.0 (USB2.0) and 100Base-T Ethernet. The KL5KUSB220 has been specifically designed to provide a simple solution to communicate with Ethernet applications accomplished by its highly integrated functionality. The USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator, Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External and Memory Interface. The SIE (Serial Interface Engine) is fully compatible with the USB2.0 specification. Our powerful internal processor enables Remote NDIS (Network Drive) which gives compatibility with next generation operating systems and faster data transfer. This USB to Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area Network), Cable Modem, Set Top Boxes, or Mobile Networking applications.
Features
* * * * * * * Advanced 16 Bit processor for USB transaction processing and control data processing 100Base-T compatibility USB interface version 2.0 compliant SIE (Serial Interface Engine) Internal Clock Generation - Utilizes low cost external 12MHz crystal circuitry MII Physical Layer interface 32KB Internal RAM buffer * * * * * * Remote NDIS for faster data transfer. Fully IEEE compliant 100 Mbit/sec Ethernet MAC Layer. Interfaces serially of an external ENDEC PHY. UART External memory interface 176 LQFP package Serial Interface for external EEPROM
Block Diagram
Txd Rxd
UART
Timer 0 Timer 1
16 Bit Processor
Watchdog Timer
A15-0
CK DIO
EEPROM Serial Interface
SRAM Interface
16 Bit Address / Data Bus
D15-0 Cntrl.
2 INT 1-0
IRQ
RAM (32KB)
Serial Interface Engine
Clock Gen. & Internal PLL
X1 X2
MII PHY Interface
100 Mb/s Ethernet Interface
Mask ROM (16 KB)
UTMI Interface
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
1
KL5KUSB220
USB2.0 to 100 Ethernet Controller Pin Diagram 176LQFP
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
VDD XD[10] XD[9] XD[8] XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] N/C VDD GND GND GND XD[1] XD[0] XA[15] XA[14] XA[13] XA[12] N/C VDD XA[11] XA[10] XA[9] XA[8] GND GND GND XA[7] XA[6] N/C VDD XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] n_XBHE n_XRAM_SEL IO[8] VDD
VDD XD[11] XD[12] XD[13] XD[14] XD[15] n_XRD n_XWR n_XROM_SEL XCVRSEL GND GND GND VDD N/C SIEDATA[0] SIEDATA[1] SIEDATA[2] SIEDATA[3] SIEDATA[4] GND GND GND VDD N/C SIEDATA[5] IO[6] SIEDATA[6] SIEDATA[7] RXACTIVE RXVALID RXERROR VDD N/C GND GND GND LINESTATE[0] LINESTATE[1] IO[10] TX_READY UTM_CLK TX_VALID VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
KL5KUSB220_L
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
VDD IO[7] IO[6] IO[5] IO[4] IO[3] IO[2] GND GND GND N/C VDD IO[1] IO[0] X_PCLK n_RESET n_TST ERXDV N/C VDD GND GND GND ERXER ETXEN ETXER N/C VDD GND GND GND VDD CP_OUT2 VCO_IN2 GND PLLEN2 VDD CP_OUT1 VCO_IN1 GNDPLL X2 CLK PLLEN1 VDD
VDD IO[11] SUSPENDM OPMODE[0] OPMODE[1] RESETOUT SIEDATA[8] SIEDATA[9] SIEDATA[10] SIEDATA[11] VDD N/C SIEDATA[12] SIEDATA[13] GND GND GND SIEDATA[14] SIEDATA[15] VALIDH X_UCLK VDD N/C TERMSEL UART_RXD UART_TXD ETXCLK ERXCLK ECRS GND GND GND VDD N/C ERXD[0] ERXD[1] ERXD[2] ERXD[3] ECOL ETXD[0] ETXD[1] ETXD[2] ETXD[3] VDD
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
2
KL5KUSB220
USB2.0 to 100 Ethernet Controller
KL5KUSB220 Application Block Diagram
USB
USB2.0 PHY
KL5KUSB220 USB / Ethernet
Ethernet PHY
Transformer
Full duplex 100 Base-T Ethernet MII Interface
Serial EEPROM Optional External Memory
Pin Description
Pin # LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 I/O PWR I/O I/O I/O I/O I/O OUT OUT OUT OUT GND GND GND VDD N/C I/O I/O I/O I/O I/O GND GND GND Pin Name VDD XD[11] XD[12] XD[13] XD[14] XD[15] n_XRD n_XWR n_XROM_SEL XCVRSEL GND GND GND VDD N/C SIEDATA[0] SIEDATA[1] SIEDATA[2] SIEDATA[3] SIEDATA[4] GND GND GND Description VDD External data 11 External data 12 External data 13 External data 14 External data 15 External memory read, active low. External memory write, active low. External ROM CS. USB Transceiver select, HS/LS.
USB data 0. USB data 1. USB data 2. USB data 3. USB data 4.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
3
KL5KUSB220
USB2.0 to 100 Ethernet Controller
Pin # LQFP 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 I/O VDD N/C I/O I/O I/O I/O IN IN IN VDD N/C GND GND GND IN IN I/O IN IN OUT VDD VDD I/O OUT OUT OUT OUT I/O I/O I/O I/O VDD N/C I/O I/O GND GND GND I/O I/O I/O OUT VDD N/C OUT IN OUT IN IN IN Pin Name VDD N/C SIEDATA[5] IO[9] SIEDATA[6] SIEDATA[7] RXACTIVE RXVALID RXERROR VDD N/C GND GND GND LINESTATE[0] LINESTATE[1] IO[10] TX_READY UTM_CLK TX_VALID VDD VDD IO[11] SUSPENDM OPMODE[0] OPMODE[1] RESETOUT SIEDATA[8] SIEDATA[9] SIEDATA[10] SIEDATA[11] VDD N/C SIEDATA[12] SIEDATA[13] GND GND GND SIEDATA[14] SIEDATA[15] VALIDH X_UCLK VDD N/C TERMSEL UART-RXD UART_TXD ETCLK ERXCLK ECRS Description
USB data 5. GPIO 9 USB data 6. USB data 7. USB receive active. USB receive data valid. USB receive error
USB Vp line USB Vm line GPIO 10 USB transceiver ready for Tx data. USB transceiver clock. USB Tx data valid for transmission.
GPIO 11 USB suspend. USB transceiver opmode0. USB transceiver opmode1. USB reset out. USB data 8. USB data 9. USB data 10. USB data 11.
USB data 12. USB data 13.
USB data 14. USB data 15. USB Tx or Rx high byte valid. USB clock out.
USB transceiver termination select. UART receive data. UART transmit data. MII transmit data. MII receive data. MII carrier sense.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
4
KL5KUSB220
USB2.0 to 100 Ethernet Controller
Pin # LQFP 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 I/O GND GND GND VDD N/C IN IN IN IN IN OUT OUT OUT OUT VDD VDD IN XIN XOUT GND IN OUT VDD IN GND IN OUT VDD GND GND GND VDD N/C OUT OUT IN GND GND GND VDD N/C IN IN IN OUT I/O I/O VDD N/C GND Pin Name GND GND GND VDD N/C ERXD[0] ERXD[1] ERXD[2] ERXD[3] ECOL ETXD[0] ETXD[1] ETXD[2] ETXD[3] VDD VDD PLLEN1 CLK X2 GND VCO_IN1 CP_OUT1 VDD PLLEN2 GND VCO_IN2 CP_OUT2 VDD GND GND GND VDD N/C ETXER ETXEN ERXER GND GND GND VDD N/C ERXDV n_TST n_RESET X_PCLK IO[0] IO[1] VDD N/C GND Description
MII receive data 0. MII receive data 1. MII receive data 2. MII receive data 3. MII collision detected. MII transmit data 0. MII transmit data 1. MII transmit data 2. MII transmit data 3.
PLL #1 enable. 12 MHz clock/crystal input. 12 MHz crystal output. PLL #1 VCO IN. PLL #1 VCO OUT. PLL #2 enable. PLL #2 VCO IN. PLL #2 VCO OUT.
MII transmit error. MII transmit enable to PHY. MII receive error.
MII receive data valid. Test pin. Reset. Processor clock. GPIO 0 GPIO 1
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
5
KL5KUSB220
USB2.0 to 100 Ethernet Controller
Pin # LQFP 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 I/O GND GND I/O I/O I/O I/O I/O I/O VDD VDD I/O OUT OUT OUT OUT OUT OUT OUT OUT VDD N/C OUT OUT GND GND GND OUT OUT OUT OUT VDD N/C OUT OUT OUT OUT I/O I/O GND GND GND VDD N/C I/O I/O I/O I/O I/O I/O I/O Pin Name GND GND IO[2] IO[3] IO[4] IO[5] IO[6] IO[7] VDD VDD IO[8] n_XRAM_SEL n_XBHE XA[0] XA[1] XA[2] XA[3] XA[4] XA[5] VDD N/C XA[6] XA[7] GND GND GND XA[8] XA[9] XA[10] XA[11] VDD N/C XA[12] XA[13] XA[14] XA[15] XD[0] XD[1] GND GND GND VDD N/C XD[2] XD[3] XD[4] XD[5] XD[6] XD[7] XD[8] Description
GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7
GPIO 8 External RAM byte low enable. External RAM byte high enable. External address 0. External address 1. External address 2. External address 3. External address 4. External address 5.
External address 6. External address 7.
External address 8. External address 9. External address 10. External address 11.
External address 12. External address 13. External address 14. External address 15. External data 0. External data 1.
External data 2. External data 3. External data 4. External data 5. External data 6. External data 7. External data 8.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
6
KL5KUSB220
USB2.0 to 100 Ethernet Controller
Pin # LQFP 174 175 176 I/O I/O I/O VDD Pin Name XD[9] XD[10] VDD External data 9. External data 10. Description
Function Description
16 Bit Processor
The integrated 16 bit processor serves as a micro controller for USB peripherals. The processor can execute approximately five million instructions per second. With this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host PC, thus improving overall performance of the system. The masked ROM (4K X 16) in the KL5KUSB220 or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and USB transaction processing. The 16-bit processor is designed for efficient data execution by having direct access to the RAM Buffer, external memory, I/O interfaces, and all the control and status registers. The divide/multiply feature expands the capability of USB peripherals. The processor supports prioritized vectored hardware interrupts. In addition, as many as 240 software interrupt vectors are available. The processor provides six addressing modes, supporting memory-to-memory, memoryto-register, register-to-register, immediate-to-register or immediate-to-memory operations. Register, direct, immediate, indirect, and indirect indexed addressing modes are supported. In addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. The processor features a full set of program control, logical, and integer arithmetic instructions. All instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. Several special " short immediate" instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction.
RAM Buffer
The USB controller contains a 32K byte internal buffer memory. The memory is used to buffer data and USB packets and accessed by the 16 Bit processor and the SIE. USB transactions are automatically routed to the memory buffer. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions. Data is read from the interface and is processed and packetized by the 16-bit I/O processor.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
7
KL5KUSB220
USB2.0 to 100 Ethernet Controller
PLL Clock Generator
A 12 MHz external crystal may be used with the KL5KUSB220 controller. Two pins, X1 and CLK, are provided to connect a lower cost crystal circuit to the device. There are two PLL's in the KL5KUSB220, one PLL is configured as a x4 multiplier and the second is configured as a x5 multiplier. The first PLL is used to generate the processor clock. The processor has the ability to select the desired processor clock to 48 MHz (default) or lower. The second PLL is used to generate the clock for the USB 2.0 SIE. Circuitry is provided to generate the internal 48MHz clock requirements of the device. If a n exteran 12 MHz clock is available in the application, it may be used in lieu of the crystal circuit vy connecting directly to the CLK input pin.
Unified Scatter Gather DMA Controller
The unified scatter gather DMA controller enables the high speed data through required for USB 2.0 to 100Mb Ethernet. The processor creates the DMA Control Blocks (DCB's) and enables reception or transmission on a channel. The unified DMA controller then receives/transmits the data to/from the corresponding buffer specified in the DCB.
USB 2.0 Interface
The KL5KUSB220 Controller has USB 2.0 SIE (Serial Interface Engine) allowing both HS (High Speed) and FS (Full Speed) operation. The controller has an interface to an external UTMI Transceiver.
10Mb, 100Mb/sec Ethernet Interface
The KL5KUSB220 Controller has a built in the Ethernet MAC (Media Access Controller) which is fully compliant with the IEEE 802.3 Ethernet standard. The KL5KUSB220 connects externally to a MII interface 10 Base -T and/or 100 Base-T PHY. The KL5KUSB220 Controller 16-bit processor has direct access to the registers of the MAC.
UART Interface
Supports a transfer rate of 7200 to 115.2K baud.
General Purpose I/O
Up to 12 general purpose I/O signals are available. However, most GPIO may be configured for special purpose functions such as UART, Serial EEPROM interface, Digital Input, etc.
Serial EEPROM Support
The USB Controller serial interface is used to provide access to external EEPROM's. The interface can support a variety of Serial EEPROM formats.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
8
KL5KUSB220
USB2.0 to 100 Ethernet Controller
SRAM Interface
An address port and 16-bit data port has been provided to interface to an external SRAM.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
9
KL5KUSB220
USB2.0 to 100 Ethernet Controller
DC CHARACTERISTICS
U2E is implemented with Kawasaki's 0.5um CMOS CBA and Embedded Memory KZ300EM Technology. The followings are the description of chip electric characteristics.
1. Absolute Maximum Ratings
Table 5.1 Absolute Maximum Ratings Parameter Symbol Ratings Supply Voltage Vdd -0.3 ~ 4.0 Input Voltage Vin -0.3 ~ 7.3 DC Output Current Iout 15 Storage Temperature Tstg -55 ~ 125 Unit V V mA C
2. Recommended Operating Conditions
Table 5.2 Recommended Operating Conditions Parameter Symbol Min Typ Operating supply voltage Vdd 3.0 - Operating ambient temperature Ta 0 - Max 3.6 70 Unit V C
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice form Kawasaki LSI February 22, 2000 * (c)Copyright 2000 * Kawasaki LSI * Printed in U.S.A
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 1.0
10

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